Title

DRAMSim2 - A cycle accurate DRAM simulator modified for row-buffer caching

Creators

Zhu Zhichun
Zhang Xiaodong
Zhao Zhang, College of William and Mary

Document Type

Data

DOI

10.24433/co.b409a73d-8b8a-441c-a64c-c062445a48d9

Publication Date

1-1-2017

Description

Reproducibility experimentation for "A permutation-based page interleaving scheme to reduce row-buffer conflicts and exploit data locality" that uses a modified DRAMSim2 to simulate SPEC CPU benchmarks with an interleaved row-buffer addressing scheme.

Related Content

10.1145/360128.360134

Publisher

Code Ocean

Recommended Citation

Zhichun, Zhu; Xiaodong, Zhang; Zhang, Zhao (2017), "DRAMSim2 - A cycle accurate DRAM simulator modified for row-buffer caching", Code Ocean, doi: 10.24433/co.b409a73d-8b8a-441c-a64c-c062445a48d9

https://doi.org/10.24433/co.b409a73d-8b8a-441c-a64c-c062445a48d9

Source Link

https://codeocean.com/2016/10/14/dramsim2-a-cycle-accurate-dram-simulator-modified-for-row-buffer-caching