Title

DRAMSim2 - A cycle accurate DRAM simulator modified for row-buffer caching

Document Type

Data

DOI

10.24433/co.b409a73d-8b8a-441c-a64c-c062445a48d9.v2

Publication Date

1-1-2018

Description

Reproducibility experimentation for "A permutation-based page interleaving scheme to reduce row-buffer conflicts and exploit data locality" that uses a modified DRAMSim2 to simulate SPEC CPU benchmarks with an interleaved row-buffer addressing scheme.

Publisher

Code Ocean

Source Link

https://codeocean.com/2018/02/08/dramsim2-a-cycle-accurate-dram-simulator-modified-for-row-buffer-caching

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